1. Field of the Invention
The present invention relates generally to a Quadrature Phase Shift Keying (QPSK) demodulator using a QPSK scheme, and in particular, to an apparatus for compensating for a phase mismatch due to a phase error between an I-channel signal and a Q-channel signal.
2. Description of the Related Art
In general, the QPSK scheme, which is an expanded concept of a Phase Shift Keying (PSK) scheme or a Binary Phase Shift Keying (BPSK) scheme in wireless communication systems, uses signals having 4 patterns.
For example, in the QPSK scheme, 2-bit digital signals having 4 patterns of ‘00,’, ‘01,’, ‘10’ and ‘11’ are used. Unlike the BPSK scheme of transmitting a broadcasting wave 180° out of phase from each other, the QPSK scheme is a scheme of generating 4 signals 90° out of phase from each other and communicating the signal through a transceiver using the 4 generated signals. As an example, a QPSK demodulator of a Code Division Multiple Access (CDMA) system using the QPSK scheme will now be described.
FIG. 1 is a diagram of a QPSK demodulator of a conventional communication system.
In general, a modulator using the QPSK scheme divides binary data into I-channel binary data and Q-channel binary data, amplitude-modulates the I-channel binary data and the Q-channel binary data using cosine and sine functions, which have a phase difference of 90°, combines the amplitude-modulated I-channel binary data and Q-channel binary data, and transmits the combined binary data. In the QPSK demodulator receiving the transmitted signal, the I- and Q-channel combined signal is mixed with carrier cosine and sine functions using a synchronous detection scheme and passes through a low pass filter (LPF).
Referring to FIG. 1, a QPSK signal is demodulated by the QPSK demodulator of the communication system using the QPSK scheme. The QPSK demodulator includes a radio frequency (RF) module for performing RF processing, which includes an automatic gain controller (AGC) 101, a first mixer 103, a first low pass filter (LPF) 105, a first analog-to-digital converter (ADC) 107, a second mixer 109, a second LPF 111, a second ADC 113, a voltage controlled oscillator (VCO) 115, and a phase shifter 117, and a baseband integrated circuit (IC) 119 for processing a baseband signal.
The AGC 101 amplifies a QPSK signal by controlling the gain of the QPSK demodulator demodulating the QPSK signal to the maintain outputs of the first ADC 107 and the second ADC 113 at desired levels.
The I-channel signal output from the AGC 101 is input to the first mixer 103, and the Q-channel signal is input to the second mixer 109. The I-channel signal is mixed with an I-channel demodulation signal received from the phase shifter 117 by the first mixer 103. The VCO 115 generates a frequency, as controlled by a voltage, and outputs the generated frequency to the phase shifter 117. The phase shifter 117 receives a local oscillation signal output from the VCO 115 and generates the I-channel demodulation signal and a Q-channel demodulation signal, which have a phase difference of 90° from each other.
The first mixer 103 receives the I-channel demodulation signal output from the phase shifter 117, mixes it with the I-channel signal, and outputs the mixed I-channel signal to the first LPF 105. The first LPF 105 receives the output signal of the first mixer 103, filters the signal, and outputs the filtered signal to the first ADC 107. The first ADC 107 receives the signal filtered by the first LPF 105, analog-to-digital converts the received signal, and outputs the digital signal to the baseband IC 119.
The Q-channel signal is mixed with the Q-channel demodulation signal received from the phase shifter 117 by the second mixer 109. The second mixer 109 receives the Q-channel demodulation signal output from the phase shifter 117, mixes it with the Q-channel signal, and outputs the mixed Q-channel signal to the second LPF 111. The second LPF 111 receives the output signal of the second mixer 109, filters the signal, and outputs the filtered signal to the second ADC 113. The second ADC 113 receives the signal filtered by the second LPF 111, converts the received analog signal to a digital signal, and outputs the converted digital signal to the baseband IC 119.
The baseband IC 119 receives the RF processed I-channel and Q-channel signals and demodulates the QPSK signal.
However, when the QPSK demodulator using the QPSK scheme is utilized, there is generated a phase mismatch due to a phase error between the I-channel signal and the Q-channel signal introduced in the phase shifter 117, or the LPF 105 or 111, or combinations thereof.
Thus, when a signal is demodulated using the I-channel signal and the Q-channel signal having the phase mismatch, the signal cannot be correctly restored. In particular, for a phase mismatch due to the phase shifter 117, a local oscillation frequency is considerably high along with an increase of use of a direct conversion demodulator without using an intermediate frequency. Accordingly, even if the I-channel demodulation signal and the Q-channel demodulation signal output from the phase shifter 117 have a small phase error, if a phase mismatch is generated due to the phase error, the phase mismatch have a negative influence upon the demodulation of the QPSK signal and makes for difficult implementation of the phase shifter 117.